The present invention generally relates to fabrication of semiconductor devices and more particularly to the art of dry etching and a fabrication process of a semiconductor device using a dry etching process.
With the advancement in the fabrication technology of miniaturized semiconductor devices and integrated circuits, efforts are being made not only to miniaturize gate electrode patterns but also various interconnection patterns used in such semiconductor devices. The Al wiring pattern used in the uppermost layer of a multilayer interconnection structure is no exception.
When forming such extremely fine wiring patterns by means of photolithography, it is generally practiced to provide an anti-reflection film of SiN or SiON between a conductor film to be patterned and a resist film during an exposure process of the resist film, for eliminating formation of optical standing waves in the resist film. After the developing process of the resist film thus exposed, the wiring pattern is formed by applying a dry etching process to the conductor film while using a resist pattern thus formed from the resist film as an etching mask.
In the process of forming extremely fine wiring patterns used in recent, so-called submicron devices, on the other hand, it is practiced to reduce the thickness of the resist film and conduct the dry etching process under a reduced pressure environment while using a high-density plasma.
On the other hand, such a dry etching process, conducted in a high-density plasma under a reduced pressure environment, raises a problem in that there tends to develop a facet or shoulder in the resist pattern used for the etching mask as represented in FIGS. 1A and 1B. It is believed that such a facet is formed by the sputtering effect of the plasma acting on the edge part of the resist pattern.
Referring to FIG. 1A, an SiO.sub.2 film 12 is formed on a Si substrate 11, and a layer 13 of Al is formed on the SiO.sub.2 film 12 as an interconnection layer. Further, the Al layer 13 is covered by an anti-reflection film 14 of SiON, and a resist film 15 is deposited on the anti-reflection film 14. The resist film 15 is then patterned according to the shape of the wiring pattern to be formed in the Al layer 13 as a result of an exposure and developing process. The resist film 15 thereby forms a resist pattern designated also by a reference numeral 15.
Next, in the step of FIG. 1B, the structure of FIG. 1A is introduced into a dry etching apparatus, and the anti-reflection film 14 and the underlying Al layer 13 are patterned consecutively to form the desired wiring pattern while using the resist pattern 15 as an etching mask.
In the foregoing photolithographic patterning process of the Al layer 13, it can be seen that the resist pattern 15 is formed with facets 15a and 15b as a result of the sputtering effect associated with the foregoing dry etching process. More specifically, the plasma used in the dry etching process acts upon the edge part of the resist pattern 15 of FIG. 1A and the facets 15a and 15b are formed as a result of erosion of the resist pattern 15 by the plasma. When such facets 15a and 15b are formed in the resist pattern 15, the resist pattern 15 is thinned out at the edge part thereof, and the width of the conductor pattern formed as a result of the dry etching process is reduced inevitably. As the resist pattern 15 is used twice, first for the patterning the anti-reflection film 14 and second for patterning of the Al layer 13, the problem of formation of the facets 15a and 15b can provide a profound effect on the patterning of the Al layer 13, particularly the width of the obtained conductor pattern.
In order to suppress the formation of the resist facets, it has been proposed to apply a curing process to the resist pattern 15 prior to the dry etching process. For example, the Japanese Laid-Open Patent Publication 4-304730 describes such a pre-curing process applied to a UV resist pattern having a photosensitivity in a ultraviolet or near-ultraviolet wavelength band such as the g-line wavelength (436 nm) or the i-line wavelength (365 nm) of Hg, wherein the pre-curing process is applied to the UV resist prior to a dry etching process that uses the UV resist as an etching mask.
FIGS. 2A-2C show an example of the photolithographic process that includes a pre-curing process of a conventional UV resist pattern, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2A showing a process corresponding to the step of FIG. 1A, the resist pattern 15 is formed as a result of the UV-exposure and developing process of the UV resist film, and the structure of FIG. 2A is incorporated into an etching chamber of a dry etching apparatus in the step of FIG. 2B. In the dry etching apparatus, a deep ultraviolet (DUV) radiation having a wavelength of about 300 nm is generated by inducing a plasma in the mixed gas of CF.sub.4 and O.sub.2 that is introduced into the etching chamber.
The UV resist forming the resist film has a structure represented by the formula (1) as ##STR1## and there occurs an excitation of .pi. electrons in the benzene ring as a result of the exposure to the foregoing DUV radiation. Thereby, the CH.sub.3 group in the resist is eliminated and the CH.sub.3 group thus eliminated causes a bridging reaction to form a structure represented by the formula (2) as ##STR2## wherein the resist film thus caused the bridging reaction and having the structure of formula (2) shows an excellent resistance against the dry etching process.
On the other hand, the foregoing process of pre-curing a UV resist pattern by way of a DUV radiation is not applicable to the recent exposure process used for the fabrication of ultrafine, submicron or sub-quarter micron semiconductor devices. It should be noted that such recent, advanced exposure processes generally use an ArF excimer layer or a KrF excimer laser for the source of DUV exposure radiation, while the UV resists do not have a satisfactory photosensitivity to the exposure wavelength of such excimer lasers. The foregoing excimer lasers produce a strong optical radiation in the DUV wavelength band.
In order to achieve an exposure process in such a DUV wavelength, it is generally practiced to use a so-called chemical amplification resist having a composition represented in formula (3) or formula (4) below, wherein the formula (3) represents the structure of the resist exposed by an ArF excimer laser (193 nm), while the formula (4) represents the structure of the resist exposed by a KrF excimer laser (248 nm). ##STR3##
Contrary to the UV resist of formula (1), it should be noted that the foregoing chemical amplification resist does not contain a group such as CH.sub.3 that makes a bonding with the .pi.-electrons of the benzene ring. In other words, the mechanism of curing is different between the foregoing chemical amplification resist and the conventional UV resist. Thus, it is not possible to obtain a desired pre-curing effect even when the pre-curing process of FIG. 2B is applied to the foregoing chemical amplification resist of the formula (3) or formula (4).
In order to avoid the problem of facet formation in the DUV resist, there is a proposal in the Japanese Laid-Open Patent Publication 7-94467 to apply an ion implantation process of Ar.sup.+ to the resist pattern 15 in the curing step of FIG. 2B under an acceleration energy of about 10 keV. Further, the foregoing Japanese Laid-Open Patent Publication 7-94467 describes a process of applying a plasma, induced in the mixed gas of CHF.sub.3 and O.sub.2, to the surface of the resist pattern 15 in the step of FIG. 2B.
FIG. 3 shows the dry etching process corresponding to the step of FIG. 2C conducted while using a chemical amplification resist according to the foregoing teaching of the Japanese Laid-Open Patent Publication in place of the resist pattern 15.
Referring to FIG. 3, the resist pattern 15 is subjected to a pre-curing process in the step corresponding to the step of FIG. 2B by conducting an ion implantation process of Ar.sup.+ into the resist pattern 15. In the illustrated example of FIG. 3, the Al layer 13 and the SiON anti-reflection film 14 thereon are patterned under the existence of a high-frequency plasma while using BCl.sub.3 and Cl.sub.2 as the etching gas.
As represented in FIG. 3, the resist pattern 15 includes, on the top surface and the side walls thereof, a resistant layer 15A as a result of the ion implantation of Ar.sup.+, wherein the resistant layer 15A has a resistance against the dry etching process and the problem of facet formation explained with reference to FIG. 1B is successfully eliminated.
On the other hand, the foregoing process has a drawback in that, because of the necessity of conducting an ion implantation process of Ar.sup.+ under the large acceleration energy as high as 10 keV, the resist pattern 15 has to be introduced, together with the substrate 11, into an ion implantation apparatus prior to the step of conducting the dry etching process. However, the use of such a separate ion implantation process increases the number of fabrication steps and hence the fabrication cost of the semiconductor device.
According to the alternate teaching of the foregoing Japanese Laid-Open Patent Publication 7-94467, the use of the separate ion implantation process can be avoided by exposing the chemical amplification resist pattern 15 to the plasma of CHF.sub.3 and O.sub.2 as noted before. In this case, too, a resistant layer similar to the resistant layer 15A is formed on the top surface and on the side walls. Thereby, the problem of facetting is effectively avoided. According to this process, the anti-reflection film 14 is patterned during the plasma processing of the resist pattern 15.
On the other hand, the foregoing process of forming the resistant layer 15A in the resist pattern 15 by the plasma process has a drawback, associated with the depositive nature of CHF.sub.3, a fluorocarbon compound, in that a carbon polymer compound tends to cause a deposition on the surface of the resist pattern 15 when such a plasma process is applied. Thus, there arises a problem of etching shift in which the width of the obtained wiring pattern tends to exceed the desired or designed width of the wiring pattern when the resist pattern 15 thus processed is used as an etching mask in the dry etching process of FIG. 2C or FIG. 3. Further, the degree of this etching shift tends to change depending on the density of the wiring patterns thus formed on the substrate.
Thus, the conventional process has a drawback in that it is difficult to form the desired wiring pattern by using a dry etching process of a conductor layer while using a chemical amplification resist pattern having a sensitivity in the DUV wavelength such that the obtained wiring pattern has a designed width irrespective of the pattern density of the wiring patterns.